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ISL78020, ISL78022
Data Sheet December 6, 2007 FN6386.2
Automotive Grade TFT-LCD DC/DC with Integrated Amplifiers
The ISL78020 and ISL78022 integrate a high performance boost regulator with 2 LDO controllers for VON and VOFF, a VON-slice circuit with adjustable delay and either one (ISL78020) or five (ISL78022) amplifiers for VCOM and VGAMMA applications. The boost converter in the ISL78020 and ISL78022 is a current mode PWM type integrating an 18V N-Channel MOSFET. Operating at 1.2MHz, this boost converter can operate in either P-Mode for superior transient response, or in PI-Mode for tighter output regulation. Using external low-cost transistors, the LDO controllers provide tight regulation for VON, VOFF, as well as providing start-up sequence control and fault protection. The amplifiers are ideal for VCOM and VGAMMA applications, with 150mA peak output current drive, 12MHz bandwidth, and 12V/s slew rate. All inputs and outputs are rail-to-rail. Available in a 32 Ld TQFP (7mmx7mm) Pb-free package, the ISL78020, ISL78022 are specified for operation over a -40C to +105C temperature range.
Features
* Current mode boost regulator - Fast transient response - 1% accurate output voltage - 18V/3A integrated FET - >90% efficiency * 2.6V to 5.5V VIN supply * 2 LDO controllers for VON and VOFF - 2% output regulation - VON-slice circuit * High speed amplifiers - 150mA short-circuit output current - 12V/s slew rate - 12MHz -3dB bandwidth - Rail-to-rail inputs and outputs * Built-in power sequencing * Internal soft-start * Multiple overload protection * Thermal shutdown * 32 Ld 7x7 TQFP package * Pb-free (RoHS compliant)
Ordering Information
PART NUMBER (Note) ISL78020ANZ* ISL78022ANZ* PART MARKING PACKAGE (Pb-Free) PKG. DWG. #
Applications
* All automotive TFT-LCD panels
ISL78020 ANZ 32 Ld 7x7 TQFP Q32.7x7 ISL78022 ANZ 32 Ld 7x7 TQFP Q32.7x7
*Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL78020, ISL78022 Pinouts
ISL78020 (32 LD TQFP) TOP VIEW
28 DRVN 26 DRVP 32 COM 32 COM 31 DRN 31 DRN 27 FBN 25 FBP 29 DEL 30 CTL
ISL78022 (32 LD TQFP) TOP VIEW
28 DRVN 26 DRVP 27 FBN 29 DEL 25 FBP 24 COMP 23 FB 22 IN 21 LX 20 OUT5 19 NEG5 18 POS5 17 OUT4 POS2 10 BGND 11 POS3 12 OUT3 13 SUP 14 POS4 15 NEG4 16
FN6386.2 December 6, 2007
SRC 1 REF 2 AGND 3 PGND 4 OUT1 5 NEG1 6 POS1 7 NC 8 IC 10 BGND 11 NC 12 NC 13 SUP 14 NC 15 NC 16 NC 9
24 COMP 23 FB 22 IN 21 LX 20 NC 19 NC 18 IC 17 NC
SRC 1 REF 2 AGND 3 PGND 4 OUT1 5 NEG1 6 POS1 7 OUT2 8 NEG2 9
NC = NOT INTERNALLY CONNECTED IC = INTERNALLY CONNECTED
2
30 CTL
ISL78020, ISL78022
Absolute Maximum Ratings (TA = +25C)
IN, CTL to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V COMP, FB, FBP, FBN, DEL, REF to AGND. . . . -0.3V to VIN + 0.3V PGND, BGND to AGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V SUP to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +18V DRVP, SRC to AGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +36V POS1, NEG1, OUT1, POS2, NEG2, OUT2, POS3, OUT3, POS4, NEG4, OUT4, POS5, OUT5 to AGND . -0.3V to VSUP + 0.3V DRVN to AGND . . . . . . . . . . . . . . . . . . . . . . .VIN -20V to VIN + 0.3V
Thermal Information
COM, DRN to AGND . . . . . . . . . . . . . . . . . . . . -0.3V to VSRC +0.3V LX Maximum Continuous RMS Output Current. . . . . . . . . . . . . 1.6A OUT1, OUT2, OUT3, OUT4, OUT5 Maximum Continuous Output Current . . . . . . . . . . . . . . . . 75mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Maximum Continuous Junction Temperature . . . . . . . . . . . . +125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curve Operating Ambient Temperature . . . . . . . . . . . . . . .-40C to +105C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER SUPPLY VIN VLOR VLOF IS ISS TFD VREF
VIN = 3V, VBOOST = VSUP = 12V, VSRC = 20V, limits over -40C to +105C temperature range, unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
Input Supply Range Undervoltage Lockout Threshold Undervoltage Lockout Threshold Quiescent Current Quiescent Current - Switching Fault Delay Time Reference Voltage VIN rising VIN falling LX not switching LX switching CDEL = 100nF TA = +25C
2.6 2.4 2.2 2.5 2.3
5.5 2.6 2.4 2.5 9.5 23 15
V V V mA mA ms
1.19 1.187
1.215 1.215 140
1.235 1.238
V V C
SHUTDN
Thermal Shutdown Temperature
MAIN BOOST REGULATOR VBOOST FOSC DCM VFBB Output Voltage Range Oscillator Frequency Maximum Duty Cycle Boost Feedback Voltage TA = +25C VIN + 15% 1050 82 1.192 1.188 VFTB FB Fault Trip Level Falling edge 50mA < ILOAD < 250mA VIN = 2.6V to 5.5V VFB = 1.35V dI = 2.5A at COMP, FB = COMP 160 160 VFB = 1.35V, VLX = 13V Duty cycle = 65% CDEL = 100nF 0.02 3.0 7 40 0.85 1200 85 1.205 1.205 0.925 0.1 0.08 500 1.218 1.222 1.020 18 1350 V kHz % V V V % %/V nA A/V m A A ms
VBOOST/IBOOST Load Regulation VBOOST/VIN IFB gmV rONLX ILEAKLX ILIMLX tSSB Line Regulation Input Bias Current FB Transconductance LX ON-Resistance LX Leakage Current LX Current Limit Soft-Start Period
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FN6386.2 December 6, 2007
ISL78020, ISL78022
Electrical Specifications
PARAMETER OPERATIONAL AMPLIFIERS VSUP ISUP VOS IB CMIR CMRR AOL VOH Supply Operating Range Supply Current per Amplifier Offset Voltage Input Bias Current Common Mode Input Range Common Mode Rejection Ratio Open Loop Gain Output Voltage High IOUT = 100A IOUT = 5mA VOL Output Voltage Low IOUT = -100A IOUT = -5mA ISC ICONT PSRR BW-3dB GBWP SR POSITIVE LDO VFBP Positive Feedback Voltage IDRVP = 100A, TA = +25C IDRVP = 100A VFTP IBP VPOS/IPOS IDRVP ILEAKP tSSP NEGATIVE LDO VFBN FBN Regulation Voltage IDRVN = 0.2mA, TA = +25C IDRVN = 0.2mA VFTN IBN VFBN Fault Trip Level Negative LDO Input Bias Current FBN Load Regulation IDRVN ILEAKN tSSN Source Current DRVN Off Leakage Current Soft-start Period VFBN rising VFBN = 250mV VDRVN = -6V, IDRVN = 2A to 20A VFBN = 500mV, VDRVN = -6V VFBP = 1.35V, VDRVP = 30V CDEL = 100nF 2 0.173 0.171 380 -50 0.5 4 0.1 7 10 0.203 0.203 430 0.233 0.235 480 50 V V mV nA % mA A ms VFBP Fault Trip Level Positive LDO Input Bias Current FBP Load Regulation Sink Current DRVP Off Leakage Current Soft-Start Period VFBP falling VFBP = 1.4V VDRVP = 25V, IDRVP = 0A to 20A VFBP = 1.1V, VDRVP = 10V VFBP = 1.4V, VDRVP = 30V CDEL = 100nF 2 1.176 1.176 0.82 -50 0.5 4 0.1 7 10 1.2 1.2 0.9 1.224 1.229 0.98 50 V V V nA % mA A ms Short-Circuit Current Continuous Output Current Power Supply Rejection Ratio -3dB Bandwidth Gain Bandwidth Product Slew Rate 60 90 VSUP -17 -16 -50 0 60 90 110 VSUP - 2 4.5 600 3 18 800 16 +50 VSUP V A mV nA V dB dB mV mV 30 150 mV mV mA mA dB MHz MHz V/s VIN = 3V, VBOOST = VSUP = 12V, VSRC = 20V, limits over -40C to +105C temperature range, unless otherwise specified. (Continued) CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
VSUP - 250 VSUP - 150 2 100 150 50 100 12 8 12
VON -SLICE CIRCUIT VLO VHI CTL Input Low Voltage CTL Input High Voltage VIN = 2.6V to 5.5V VIN = 2.6V to 5.5V 0.6VIN 0.4VIN V V
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FN6386.2 December 6, 2007
ISL78020, ISL78022
Electrical Specifications
PARAMETER ILEAKCTL tDrise VIN = 3V, VBOOST = VSUP = 12V, VSRC = 20V, limits over -40C to +105C temperature range, unless otherwise specified. (Continued) CONDITIONS CTL = AGND or IN 1k from DRN to 8V, VCTL = 0V to 3V step, no load on OUT, measured from VCTL = 1.5V to OUT = 20% 1k from DRN to 8V, VCTL = 3V to 0V step, no load on OUT, measured from VCTL = 1.5V to OUT = 80% MIN -1 100 TYP MAX 1 UNIT A ns
DESCRIPTION CTL Input Leakage Current CTL to OUT Rising Prop Delay
tDfall
CTL to OUT Falling Prop Delay
100
ns
VSRC ISRC
SRC Input Voltage Range SRC Input Current Start-up sequence not completed Start-up sequence completed 150 150 5 30 350 1000
30 250 350 12 60 1800
V A A
rONSRC rONDRN rONCOM SEQUENCING tON tDEL1 tDEL2 tDEL3
SRC ON-Resistance DRN ON-Resistance COM to GND ON-Resistance
Start-up sequence completed Start-up sequence completed Start-up sequence not completed
Turn-On Delay
CDEL = 100nF (See Figure 22)
10 10 10 10
ms ms ms ms
Delay Between VBOOST and VOFF CDEL = 100nF (See Figure 22) Delay Between VON and VOFF Delay From VON to VON-slice Enabled CDEL = 100nF (See Figure 22) CDEL = 100nF (See Figure 22)
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FN6386.2 December 6, 2007
ISL78020, ISL78022 Pin Descriptions
PIN NAME SRC REF AGND PGND OUT1 NEG1 POS1 OUT2 NEG2 POS2 BGND POS3 NEG3 OUT3 SUP POS4 NEG4 OUT4 POS5 NEG5 OUT5 LX IN FB COMP FBP DRVP FBN DRVN DEL CTL DRN COM ISL78022 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ISL78020 1 2 3 4 5 6 7 11 14 21 22 23 24 25 26 27 28 29 30 31 32 PIN FUNCTION Upper reference voltage for switch output Internal reference bypass terminal Analog ground for boost converter and control circuitry Power ground for boost switch Operational amplifier 1 output Operational amplifier 1 inverting input Operational amplifier 1 non-inverting input Operational amplifier 2 output Operational amplifier 2 inverting input Operational amplifier 2 non-inverting input Operational amplifier ground Operational amplifier 3 non-inverting input Operational amplifier 3 inverting input Operational amplifier 3 output Amplifier positive supply rail. Bypass to BGND with 0.1F capacitor Operational amplifier 4 non-inverting input Operational amplifier 4 inverting input Operational amplifier 4 output Operational amplifier 5 non-inverting input Operational amplifier 5 inverting input Operational amplifier 5 output Main boost regulator switch connection Main supply input; bypass to AGND with 1F capacitor Main boost feedback voltage connection Error amplifier compensation pin Positive LDO feedback connection Positive LDO transistor drive Negative LDO feedback connection Negative LDO transistor driver Connection for switch delay timing capacitor Input control for switch output Lower reference voltage for switch output Switch output; when CTL = 1, COM is connected to SRC through a 15 resistor; when CTL = 0, COM is connected to DRN through a 30 resistor
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FN6386.2 December 6, 2007
ISL78020, ISL78022 Typical Performance Curves TA = +25C, unless otherwise specified.
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 200 400 600 800 1000 1200 VIN = 3V EFFICIENCY (%) VIN = 5V 94 92 90 88 86 84 82 80 78 0 200 400 600 800 1000 1200 VIN = 3V VIN = 5V
LOAD CURRENT (mA)
LOAD CURRENT (mA)
FIGURE 1. BOOST EFFICIENCY AT VOUT = 12V (PI-MODE)
FIGURE 2. BOOST EFFICIENCY AT VOUT = 12V (P-MODE)
0 LOAD REGULATION (%) LOAD REGULATION (%) -0.1 -0.2 -0.3 -0.4 VIN = 5V -0.5 -0.6 0 200 400 600 800 1000 1200 LOAD CURRENT (mA) VIN = 3V
0 -2 -4 -6 -8 -10 -12 -14 0 200 400 600 800 1000 1200 LOAD CURRENT (mA) VIN = 3.3V VIN = 5.0V
FIGURE 3. BOOST LOAD REGULATION vs LOAD CURRENT (PI-MODE)
FIGURE 4. BOOST LOAD REGULATION vs LOAD CURRENT (P-MODE)
0.12 LINE REGULATION (%) LINE REGULATION (%) 0.10 0.08 0.06 0.04 0.02 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 INPUT VOLTAGE (V)
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 INPUT VOLTAGE (V)
FIGURE 5. BOOST LINE REGULATION vs INPUT VOLTAGE (PI-MODE)
FIGURE 6. BOOST LINE REGULATION vs INPUT VOLTAGE (P-MODE)
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FN6386.2 December 6, 2007
ISL78020, ISL78022 Typical Performance Curves TA = +25C, unless otherwise specified. (Continued)
0 BOOST OUTPUT VOLTAGE (AC COUPLING) LOAD REGULATION (%) -0.05 -0.10 -0.15 -0.20 -0.25 5 10 15 20 25 30 VON LOAD CURRENT (mA) VON = 20V
BOOST OUTPUT CURRENT
VBOOST = 12V COUT = 30F
FIGURE 7. BOOST PULSE LOAD TRANSIENT RESPONSE
FIGURE 8. VON LOAD REGULATION
0 LOAD REGULATION (%) LINE REGULATION (%) -0.02 -0.04 -0.06 -0.08 -0.10 -0.12 20 VON = 20V ILOAD = 20mA 21 22 23 24 INPUT VOLTAGE (V) 25 26
0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 5 10 15 20
VOFF = -8V
25
30
LOAD CURRENT (mA)
FIGURE 9. VON LINE REGULATION
FIGURE 10. VOFF LOAD REGULATION
0 LINE REGULATION (%) -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -15 VOFF = -8V ILOAD = 50mA -14 -13 -12 -11 -10 TIME (20ms/DIV)
VCDEL VBOOST
VOFF VON
INPUT VOLTAGE (V)
FIGURE 11. VOFF LINE REGULATION
FIGURE 12. START-UP SEQUENCE
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FN6386.2 December 6, 2007
ISL78020, ISL78022 Typical Performance Curves TA = +25C, unless otherwise specified. (Continued)
INPUT VOLTAGE VBOOST INPUT
VOFF VON
OUTPUT
TIME (20ms/DIV)
TIME (50s/DIV)
FIGURE 13. START-UP SEQUENCE
FIGURE 14. OP AMP RAIL-TO-RAIL INPUT/OUTPUT
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD TQFP SOLDERED TO PCB PER JESD51-5 1.8 POWER DISSIPATION (W) 1.5 1.2 0.9 0.6 0.3 0 0 25 50 75 100 125 150 AMBIENT TEMPERATURE (C) 1.613W TQFP32 JA = +62C/W
FIGURE 15. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Applications Information
The ISL78020 and ISL78022 provide a highly integrated multiple output power solution for TFT-LCD applications. The system consists of one high efficiency boost converter and two low cost linear-regulator controllers (VON and VOFF) with multiple protection functions. The block diagram of the whole part is shown in Figure 16. Table 1 lists the recommended components. The ISL78020 and ISL78022 integrate an N-Channel MOSFET in boost converter to minimize the external component counts and cost. The VON, VOFF linear-regulators are independently regulated by using external resistors. To achieve higher voltage than VBOOST, one or multiple stage charge pumps may be used.
TABLE 1. RECOMMENDED TYPICAL APPLICATION DIAGRAM COMPONENTS DESIGNATION C1, C2, C3 D1 DESCRIPTION 10F, 16V X5R ceramic capacitor (1210) TDK C3216X5R0J106K 1A, 20V low leakage Schottky rectifier (CASE 457-04) ON SEMI MBRM120ET3
D11, D12, D21 200mA, 30V Schottky barrier diode (SOT-23) Fairchild BAT54S L1 Q11 Q21 6.8H, 1.3A Inductor TDK SLF6025T-6R8M1R3-PF 200mA, 40V PNP amplifier (SOT-23) Fairchild MMBT3906 200mA, 40V NPN amplifier (SOT-23) Fairchild MMBT3904
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FN6386.2 December 6, 2007
ISL78020, ISL78022
VREF
REFERENCE GENERATOR
OSCILLATOR COMP OSC LX BUFFER
SLOPE COMPENSATION
FBB GM AMPLIFIER CINT VOLTAGE AMPLIFIER
PWM LOGIC CONTROLLER
CURRENT AMPLIFIER UVLO COMPARATOR CURRENT REF CURRENT LIMIT COMPARATOR SHUTDOWN AND START-UP CONTROL THERMAL SHUTDOWN UVLO COMPARATOR SS DRVN BUFFER + 0.2V VREF SS + BUFFER
PGND
DRVP
FBP
FBN 0.4V UVLO COMPARATOR
FIGURE 16. BLOCK DIAGRAM
Boost Converter
The main boost converter is a current mode PWM converter operating at a fixed frequency. The 1.2MHz switching frequency enables the use of low profile inductor and multilayer ceramic capacitors, which results in a compact, low cost power system for LCD panel design. The boost converter can operate in continuous or discontinuous inductor current mode. The ISL78020 and ISL78022 are designed for continuous current mode, but they can also operate in discontinuous current mode at light load. In continuous current mode, current flows continuously in the inductor during the entire switching cycle in steady state operation. The voltage conversion ratio in continuous current mode is given by Equation 1:
V BOOST 1 ----------------------- = -----------1-D V IN (EQ. 1)
Figure 17 shows the block diagram of the boost controller. It uses a summing amplifier architecture consisting of GM stages for voltage feedback, current feedback and slope compensation. A comparator looks at the peak inductor current cycle by cycle and terminates the PWM cycle if the current limit is reached. An external resistor divider is required to divide the output voltage down to the nominal reference voltage. Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 60k is recommended. The boost converter output voltage is determined by Equation 2:
R1 + R2 V BOOST = -------------------- x V REF R1 (EQ. 2)
Where D is the duty cycle of switching MOSFET. 10
FN6386.2 December 6, 2007
ISL78020, ISL78022
The current through MOSFET is limited to 3A peak. This restricts the maximum output current based on Equation 3:
I L V IN I OMAX = I LMT - -------- x -------- 2 VO (EQ. 3)
Where IL is peak to peak inductor ripple current, and is set by Equation 4:
V IN D I L = --------- x ---L fS (EQ. 4)
where fS is the switching frequency.
SHUTDOWN AND START-UP CONTROL CLOCK
SLOPE COMPENSATION
IFB CURRENT AMPLIFIER IREF PWM LOGIC BUFFER
LX
IFB FBB GM AMPLIFIER IREF
VOLTAGE AMPLIFIER REFERENCE GENERATOR
COMP
PGND
FIGURE 17. THE BLOCK DIAGRAM OF THE BOOST CONTROLLER
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FN6386.2 December 6, 2007
ISL78020, ISL78022
Table 2 gives typical values (margins are considered 10%, 3%, 20%, 10% and 15% on VIN, VO, L, fS and ILMT:
TABLE 2. TYPICAL VIN, VO, L, fS, AND IOMAX VALUES VIN (V) 3.3 3.3 3.3 5 5 5 VO (V) 9 12 15 9 12 15 L (H) 6.8 6.8 6.8 6.8 6.8 6.8 fS (MHz) 1.2 1.2 1.2 1.2 1.2 1.2 IOMAX (mA) 898 622 458 1360 944 694
For low ESR ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. The voltage rating of the output capacitor should be greater than the maximum output voltage.
NOTE: Capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across them increases. COUT in Equation 7 assumes the effective value of the capacitor at a particular voltage and not the manufacturer's stated value, measured at 0V.
Compensation
The ISL78020 and ISL78022 can operate in either P-Mode or PI-Mode. P-mode may be preferred in applications where excellent transient load performance is required but regulation is not critical. Connecting COMP pin directly to VIN will enable P-Mode; for better load regulation, use PI-Mode with a 2.2nF capacitor and a 180 resistor in series between COMP pin and ground. To improve the transient response, either the resistor value can be increased or the capacitor value can be reduced, but too high resistor value or too low capacitor value will reduce loop stability. Figures 3 through 6 show a comparison of P-Mode vs PI-Mode performance.
Input Capacitor
The input capacitor is used to supply the current to the converter. It is recommended that CIN be larger than 10F. The reflected ripple voltage will be smaller with larger CIN. The voltage rating of input capacitor should be larger than maximum input voltage.
Boost Inductor
The boost inductor is a critical part, which influences the output voltage ripple, transient response, and efficiency. Value of 3.3H to 10H inductor is recommended in applications to fit the internal slope compensation. The inductor must be able to handle the following average and peak current shown in Equations 5 and 6:
I L I LPK = I LAVG + -------2 IO I LAVG = -----------1-D (EQ. 5)
Boost Feedback Resistors
As the boost output voltage, VBOOST, is reduced below 12V the effective voltage feedback in the IC increases the ratio of voltage to current feedback at the summing comparator because R2 decreases relative to R1. To maintain stable operation over the complete current range of the IC, the voltage feedback to the FBB pin should be reduced proportionally, as VBOOST is reduced, by means of a series resistor-capacitor network (R7 and C7) in parallel with R1, with a pole frequency (fp) set to approximately 10kHz for C2 (effective) = 10F and 4kHz for C2 (effective) = 30F.
1 1 -1 R 7 = --------------------- - ------ 0.1 x R R 2 1 (EQ. 8)
(EQ. 6)
Rectifier Diode
A high-speed diode is desired due to the high switching frequency. Schottky diodes are recommended because of their fast recovery time and low forward voltage. The rectifier diode must meet the output current and peak inductor current requirements.
1 C 7 = ------------------------------------------------2 x 3.142 x fp x R 7
(EQ. 9)
Output Capacitor
The output capacitor supplies the load directly and reduces the ripple voltage at the output. Output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the ESR of output capacitor, and the charging and discharging of the output capacitor.
IO V O - V IN 1 V RIPPLE = I LPK x ESR + ----------------------- x --------------- x ---f C V
O OUT
Linear-Regulator Controllers (VON and VOFF)
The ISL78020 and ISL78022 include 2 independent linear-regulator controllers, in which there is one positive output voltage (VON), and one negative voltage (VOFF). The VON and VOFF linear-regulator controller function diagram, application circuit and waveforms are shown in Figures 18 and 19 respectively.
(EQ. 7)
S
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FN6386.2 December 6, 2007
ISL78020, ISL78022
VBOOST 0.1F 0.9V PG_LDOP + LDO_ON CP (TO 36V) RBP 700 DRVP FBP + GMP 1: Np RP1 RP2 20k 0.1F VON (TO 35V) CON LX
36V ESD CLAMP
The VOFF power supply is used to power the negative supply of the row driver in the LCD panel. The DC/DC consists of an external diode-capacitor charge pump powered from the inductor (LX) of the boost converter, followed by a low dropout linear regulator (LDO_OFF). The LDO_OFF regulator uses an external NPN transistor as the pass element. The on-board LDO controller is a wide band (>10MHz) transconductance amplifier capable of 5mA output current, which is sufficient for up to 50mA or more output current under the low dropout condition (forced beta of 10). Typical VOFF voltage supported by ISL78020 and ISL78022 ranges from -5V to -25V. A fault comparator is also included for monitoring the output voltage. The undervoltage threshold is set at 200mV above the 0.2V reference level.
Set-up Output Voltage
Refer to "Typical Application Circuit" on page 18, the output voltages of VON, VOFF and VLOGIC are determined by Equations 10 and 11:
R 12 V ON = V REF x 1 + --------- R 11 R 22 V OFF = V REFN + --------- x ( V REFN - V REF ) R
21
FIGURE 18. VON FUNCTIONAL BLOCK DIAGRAM
(EQ. 10)
LX 0.1F
(EQ. 11)
CP (TO -26V) LDO_OFF PG_LDON 0.4V FBN 1: Nn + VREF RN2 20k 0.1F
Where: VREF = 1.2V, VREFN = 0.2V.
High Charge Pump Output Voltage (>36V) Applications
In the applications where the charge pump output voltage is over 36V, an external NPN transistor needs to be inserted in between the DRVP pin and the base of pass transistor Q3 as shown in Figure 20, or the linear regulator can control only one stage charge pump and regulate the final charge pump output, as shown in Figure 21.
VIN CHARGE PUMP OR VBOOST OUTPUT 700
RN1 VOFF (TO -20V)
+ GMN 36V ESD CLAMP
DRVN RBN 700
COFF
FIGURE 19. VOFF FUNCTIONAL BLOCK DIAGRAM
DRVP
Q11 NPN CASCODE TRANSISTOR VON
The VON power supply is used to power the positive supply of the row driver in the LCD panel. The DC/DC consists of an external diode-capacitor charge pump powered from the inductor (LX) of the boost converter, followed by a low dropout linear regulator (LDO_ON). The LDO_ON regulator uses an external PNP transistor as the pass element. The on-board LDO controller is a wide band (>10MHz) transconductance amplifier capable of 5mA output current, which is sufficient for up to 50mA or more output current under the low dropout condition (forced beta of 10). Typical VON voltage supported by ISL78020 and ISL78022 ranges from +15V to +36V. A fault comparator is also included for monitoring the output voltage. The undervoltage threshold is set at 25% below the 1.2V reference.
ISL7802x
FBP
FIGURE 20. CASCODE NPN TRANSISTOR CONFIGURATION FOR HIGH CHARGE PUMP OUTPUT VOLTAGE (>36V)
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FN6386.2 December 6, 2007
ISL78020, ISL78022
LX 0.1F 0.1F 700 0.1F DRVP 0.47F ISL78022 Q11 VON 0.1F (>36V) 0.1F VBOOST
FBP
0.22F
FIGURE 21. THE LINEAR REGULATOR CONTROLS ONE STAGE OF CHARGE PUMP
Calculation of the Linear Regulator Base-emitter Resistors (RBP and RBN)
For the pass transistor of the linear regulator, low frequency gain (Hfe) and unity gain frequency (fT) are usually specified in the datasheet. The pass transistor adds a pole to the loop transfer function at fp = fT/Hfe. Therefore, in order to maintain phase margin at low frequency, the best choice for a pass device is often a high frequency, low gain switching transistor. Further improvement can be obtained by adding a base-emitter resistor RBE (RBP, RBL, RBN in the "Functional Block Diagram" on page 13), which increases the pole frequency to: fp = fT*(1+ Hfe *re/RBE)/Hfe, where re = KT/qIc. Thus, choose the lowest value RBE in the design as long as there is still enough base current (IB) to support the maximum output current (IC). We will take as an example the VON linear regulator. If a Fairchild MMBT3906 PNP transistor is used as the external pass transistor (Q11 in the "Typical Application Circuit" on page 18) then for a maximum VON operating requirement of 50mA the data sheet indicates Hfe_min = 60. The base-emitter saturation voltage is: Vbe_max = 0.7V. For the ISL78020 and ISL78022, the minimum drive current is shown in Equation 12:
I DRVP ( MIN ) = 2mA (EQ. 12)
Charge Pump
To generate an output voltage higher than VBOOST, single or multiple stages of charge pumps are needed. The number of stages is determined by the input and output voltage for positive charge pump stages in Equation 14:
V OUT + V CE - V INPUT N POSITIVE ------------------------------------------------------------V INPUT - 2 x V F (EQ. 14)
where VCE is the dropout voltage of the pass component of the linear regulator. It ranges from 0.3V to 1V depending on the transistor selected. VF is the forward-voltage of the charge-pump rectifier diode. The number of negative charge-pump stages is given by Equation 15:
V OUTPUT + V CE N NEGATIVE -----------------------------------------------V INPUT - 2 x V F (EQ. 15)
To achieve high efficiency and low material cost, the lowest number of charge-pump stages, which can meet the above requirements, is always preferred.
Charge Pump Output Capacitors
A ceramic capacitor with low ESR is recommended. With ceramic capacitors, the output ripple voltage is dominated by the capacitance value. The capacitance value can be chosen by Equation 16:
I OUT C OUT -----------------------------------------------------2 x V RIPPLE x f OSC (EQ. 16)
The minimum base-emitter resistor, RBP, can now be calculated as:
( RBP MIN = VBE MAX ) 0.7V ------------------------------------------------------------ = ----------------------------------- = 600 2mA - 50mA I DRVP ( MIN ) - Ic ----------------------------------------------------------------------------60 Hfe MIN (EQ. 13)
where fOSC is the switching frequency.
This is the minimum value that can be used; (choose a convenient value greater than this minimum value, i.e.: 700). Larger values may be used to reduce quiescent current, however, regulation may be adversely affected by supply noise if RBP is made too high in value. 14
Discontinuous/Continuous Boost Operation and its Effect on the Charge Pumps
The ISL78020 and ISL78022 VON and VOFF architecture uses LX switching edges to drive diode charge pumps from
FN6386.2 December 6, 2007
ISL78020, ISL78022
which LDO regulators generate the VON and VOFF supplies. It can be appreciated that should a regular supply of LX switching edges be interrupted, (for example during discontinuous operation at light boost load currents), then this may affect the performance of VON and VOFF regulation (depending on their exact loading conditions at the time). To optimize VON/VOFF regulation, the boundary of discontinuous/continuous operation of the boost converter can be adjusted, by suitable choice of inductor given VIN, VOUT, switching frequency and the VBOOST current loading, to be in continuous operation. The following equation gives the boundary between discontinuous and continuous boost operation. For continuous operation (LX switching every clock cycle) we require that:
I ( V BOOST_load ) > D * ( 1 - D ) * V IN ( 2 * L * f OSC ) (EQ. 17)
22nF to 1F and should not be more than five times the capacitor on CDEL to ensure correct start-up operation. The CDEL capacitor is typically 100nF and has a usable range from 22nF minimum to several microfarads (only limited by the leakage in the capacitor reaching A levels). CDEL should be at least 1/5 of the value of CREF (see Figure 22). Note that with 100nF on CDEL the fault time-out will be typically 23ms and the use of a larger/smaller value will vary this time proportionally (e.g. 1F will give a fault time-out period of typically 230ms).
Fault Sequencing
The ISL78020 and ISL78022 have an advanced fault detection system, which protects the IC from both adjacent pin shorts during operation and shorts on the output supplies. A high quality layout/design of the PCB, in respect of grounding quality and decoupling is necessary to avoid falsely triggering the fault detection scheme (especially during start-up). The user is directed to the layout guidelines and component selection sections to avoid problems during initial evaluation and prototype PCB generation.
where the duty cycle, D = (VBOOST - VIN)/VBOOST For example, with VIN = 5V, fOSC = 1.2MHz and VBOOST = 12V we find continuous operation of the boost converter can be guaranteed for: L = 10H and I(VBOOST) > 51mA L = 6.8H and I(VBOOST) > 74mA L = 3.3H and I(VBOOST) > 153mA
VON -Slice Circuit
The VON-slice Circuit functions as a three way multiplexer, switching the voltage on COM between ground, DRN and SRC, under control of the start-up sequence and the CTL pin. During the start-up sequence, COM is held at ground via an NDMOS FET, with ~1k impedance. Once the start-up sequence has completed, CTL is enabled and acts as a multiplexer control such that if CTL is low, COM connects to DRN through a 5 internal MOSFET, and if CTL is high, COM connects to SRC via a 30 MOSFET. The slew rate of start-up of the switch control circuit is mainly restricted by the load capacitance at COM pin as in Equation 18:
Vg V ------- = ----------------------------------( R i || R L ) * C L t (EQ. 18)
Start-up Sequence
Figure 22 shows a detailed start-up sequence waveform. For a successful power-up, there should be 6 peaks at VCDEL. When a fault is detected, the device will latch off until either EN is toggled or the input supply is recycled. When the input voltage is higher than 2.4V, an internal current source starts to charge CCDEL. During the initial slow ramp, the device checks whether there is a fault condition. If no fault is found during the initial ramp, CCDEL is discharged after the first peak. VREF turns on at the peak of the first ramp. Initially the boost is not enabled so VBOOST rises to VINVDIODE through the output diode. Hence, there is a step at VBOOST during this part of the start-up sequence. VBOOST soft-starts at the beginning of the third ramp, and is checked at the end of this ramp. The soft-start ramp depends on the value of the CDEL capacitor. For CDEL of 100nF, the soft-start time is ~7ms. VOFF turns on at the start of the fourth peak. VON is enabled at the beginning of the sixth ramp. VOFF and VON are checked at end of this ramp.
Where Vg is the supply voltage applied to the switch control circuit, Ri is the resistance between COM and DRN or SRC including the internal MOSFET rDS(ON), the trace resistance and the resistor inserted, RL is the load resistance of the switch control circuit, and CL is the load capacitance of the switch control circuit. In the "Typical Application Circuit" on page 18, R8, R9 and C8 give the bias to DRN based on Equation 19:
V ON * R 9 + A VDD * R 8 V DRN = -----------------------------------------------------------R8 + R9 (EQ. 19)
Where: R10 can be adjusted to adjust the slew rate.
Component Selection for Start-up Sequencing and Fault Protection
The CREF capacitor is typically set at 220nF and is required to stabilize the VREF output. The range of CREF is from 15
Op Amps
The ISL78020 and ISL78022 have 1 and 5 amplifiers respectively. The op amps are typically used to drive the
FN6386.2 December 6, 2007
ISL78020, ISL78022
TFT-LCD backplane (VCOM) or the gamma-correction divider string. They feature rail-to-rail input and output capability, they are unity gain stable, and have low power consumption (typical 600A per amplifier). The ISL78020 and ISL78022 have a -3dB bandwidth of 12MHz while maintaining a 10V/s slew rate.
Short Circuit Current Limit
The ISL78020 and ISL78022 will limit the short circuit current to 180mA if the output is directly shorted to the positive or the negative supply. If an output is shorted for a long time, the junction temperature will trigger the Over-Temperature Protection limit and hence the part will shut down.
FAULT DETECTED NORMAL OPERATION VON SOFT-START CHIP DISABLED FAULT PRESENT
VBOOST SOFT-START
VREF ON
VCDEL
IN
VREF
VBOOST
tON
tDEL1 VOFF tDEL2
VON
VON SLICE CIRCUIT tDEL3 NOTE: Not to scale START-UP SEQUENCE TIMED BY CDEL
FIGURE 22. START-UP SEQUENCE
16
VOFF ON
FN6386.2 December 6, 2007
ISL78020, ISL78022
Driving Capacitive Loads
ISL78020 and ISL78022 can drive a wide range of capacitive loads. As load capacitance increases, however, the -3dB bandwidth of the device will decrease and the peaking will increase. The amplifiers drive 10pF loads in parallel with 10k with just 1.5dB of peaking, and 100pF with 6.4dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5 and 50) can be placed in series with the output. However, this will obviously reduce the gain. Another method of reducing peaking is to add a "snubber" circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 150 and 10nF are typical. The advantage of a snubber is that it does not draw any DC load current and reduce the gain. There are some general guidelines for layout: 1. Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. Place VREF and VDD bypass capacitors close to the pins. 3. Reduce the loop with large AC amplitudes and fast slew rate. 4. The feedback network should sense the output voltage directly from the point of load, and be as far away from LX node as possible. 5. The power ground (PGND) and signal ground (SGND) pins should be connected at only one point. 6. The exposed die plate, on the underneath of the package, should be soldered to an equivalent area of metal on the PCB. This contact area should have multiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC. 7. To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bottom and top PCB areas especially should be maximized to allow thermal dissipation to the surrounding air. 8. A signal ground plane, separate from the power ground plane and connected to the power ground pins only at the exposed die plate, should be used for ground return connections for feedback resistor networks (R1, R11, R41) and the VREF capacitor, C22, the CDELAY capacitor C7 and the integrator capacitor C23. 9. Minimize feedback input track lengths to avoid switching noise pick-up. A demo board is available to illustrate the proper layout implementation.
Over-Temperature Protection
An internal temperature sensor continuously monitors the die temperature. In the event that the die temperature exceeds the thermal trip point, the device will be latched off until either the input supply voltage or enable is cycled.
Layout Recommendation
The device's performance including efficiency, output noise, transient response and control loop stability is dramatically affected by the PCB layout. PCB layout is critical, especially at high switching frequency.
17
FN6386.2 December 6, 2007
ISL78020, ISL78022 Typical Application Circuit
D11 0.1F VCP
D21 VCN VIN (2.6V TO 5.5V) 10F C1 10 IN FB 470nF BOOST L1 6.8H LX 0.1F 0.1F
D12
0.1F
D1 C2-C3 R2 64.9k
AVDD (9V) 10Fx2
R1 10.2k PGND
R7 OPEN C7 OPEN
180 COMP 700 VCN 0.1F Q21 DRVN NEG REG POS REG 2.2nF GND DRVP 700
VCP Q11 0.1F VON (24.5V)
VNEG (-8V)
R22
82k 10k
FBN
FBP
R12 R11
182k 470nF 9.76k
470nF R21
REF REF 0.1F CONTROL INPUT CTL DEL SW CTL COM SRC TO GATE DRIVER IC R8 68k R9 1k AVDD C8 0.1F + OUT3 OP3 VCOM POS3 VCOM SET VMAIN VGAMMA FB4 OUT4 VGAMMA4 POS4 VGAMMA SET4 NEG2 VGAMMA FB2 OUT2 VGAMMA2 POS2 VGAMMA SET2 AGND OP2 + + OUT1 OP1 VGAMMA1 POS1 VGAMMA SET1 NEG1 VGAMMA FB1 OP4 + + OUT5 OP5 VGAMMA3 POS5 VGAMMA SET3 AVDD NEG4 NEG5 VGAMMA FB3
100nF
DRN
R10 1k
18
FN6386.2 December 6, 2007
ISL78020, ISL78022 Thin Plastic Quad Flatpack Packages (TQFP)
Q32.7x7 (JEDEC MS-026ABA ISSUE B) 32 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE
D D1 -D-
INCHES SYMBOL A A1
-B-
MILLIMETERS MIN 0.05 0.95 0.30 0.30 8.90 6.90 8.90 6.90 0.45 32 0.80 BSC MAX 1.20 0.15 1.05 0.45 0.40 9.10 7.10 9.10 7.10 0.75 NOTES 6 3 4, 5 3 4, 5 7 Rev. 0 10/06
MIN 0.002 0.038 0.012 0.012 0.350 0.272 0.350 0.272 0.018 32
MAX 0.047 0.005 0.041 0.018 0.016 0.358 0.280 0.358 0.280 0.029
-A-
A2 b
E E1
b1 D D1 E
e
PIN 1 SEATING A PLANE 0.08 0.003 -C-
E1 L N e NOTES:
-H-
0.031 BSC
1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- . 4. Dimensions D1 and E1 to be determined at datum plane -H- . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm (0.003 inch). 7. "N" is the number of terminal positions.
0.08 0.003 M 11o-13o 0.020 0.008 MIN 0o MIN GAGE PLANE L 0o-7o 0.25 0.010 11o-13o A2 A1
C A-B S
DS b b1
0.09/0.16 0.004/0.006 BASE METAL WITH PLATING 0.09/0.20 0.004/0.008
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 19
FN6386.2 December 6, 2007

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